1. Field of the Invention
This invention is related to the field of computer systems and, more particularly, to coherence mechanisms in computer systems.
2. Description of the Related Art
Historically, shared memory multiprocessing systems have implemented hardware coherence mechanisms. The hardware coherence mechanisms ensure that updates (stores) to memory locations by one processor (or one process, which may be executed on different processors at different points in time) are consistently observed by all other processors that read (load) the updated memory locations according to a specified ordering model. Implementing coherence may aid the correct and predictable operation of software in a multiprocessing system. While hardware coherence mechanisms simplify the software that executes on the system, the hardware coherence mechanisms may be complex and expensive to implement (especially in terms of design time). Additionally, if errors in the hardware coherence implementation are found, repairing the errors may be costly (if repaired via hardware modification) or limited (if software workarounds are used).
One of the most difficult aspects of many hardware coherence mechanisms has to do with handling cache evictions of data (often referred to as writebacks). The data is in a state of transition, and may be in one of many locations between the source cache and its destination (another cache or the memory system). Numerous race conditions may exist between the coherence activity that is attempting to locate the most recent updates to the data and the progress of the writeback. The problem is particularly complex in distributed shared memory systems, where the writeback operation and data may need to be transferred to another node. The transfer may have a high latency, and may also introduce additional locations (e.g. buffers) at which the writeback may be found along the path.
Other systems have used a purely software approach to the issue of shared memory. Generally, the hardware in such systems makes no attempt to ensure that the data for a given memory access (particularly loads) is the most up to date. Software must ensure that non-updated copies of data are invalidated in various caches if coherent memory access is desired. While software mechanisms are more easily repaired if an error is found and are more flexible if changing the coherence scheme is desired, they typically have much lower performance than hardware mechanisms.